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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-30 17:02:20 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-30 17:02:20 -0700 |
| commit | 1b96d29174d7c56a14031bc117a7da5fa5192c81 (patch) | |
| tree | 50b8f3748b084ef3e12af58bfdf9bafa0e3880db /passes | |
| parent | 390b960c8c646018c1f6cddfec5fc2d528d42fa4 (diff) | |
| download | yosys-1b96d29174d7c56a14031bc117a7da5fa5192c81.tar.gz yosys-1b96d29174d7c56a14031bc117a7da5fa5192c81.tar.bz2 yosys-1b96d29174d7c56a14031bc117a7da5fa5192c81.zip | |
No need to punch ports at all
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9.cc | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index ce057566c..777ec6ac8 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -1121,19 +1121,6 @@ struct Abc9Pass : public Pass { Pass::call_on_module(design, derived_module, "proc"); SigMap derived_sigmap(derived_module); - Wire *currQ = derived_module->wire("\\$currQ"); - if (currQ == NULL) - log_error("'\\$currQ' is not a wire present in module '%s'.\n", log_id(cell->type)); - log_assert(!currQ->port_output); - if (!currQ->port_input) { - currQ->port_input = true; - derived_module->ports.push_back(currQ->name); - currQ->port_id = GetSize(derived_module->ports); -#ifndef NDEBUG - derived_module->check(); -#endif - } - SigSpec pattern; SigSpec with; for (auto &conn : cell->connections()) { |