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| author | Clifford Wolf <clifford@clifford.at> | 2016-11-09 13:13:26 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-11-09 13:13:26 +0100 |
| commit | 1827a4896475efae6a88b18bad8787bcea7c6a92 (patch) | |
| tree | eed9844a47b8a610e4027f7def6fd1c0239ac586 /passes | |
| parent | 617693e69128982ce1be91b76c541d6ae1950ad8 (diff) | |
| download | yosys-1827a4896475efae6a88b18bad8787bcea7c6a92.tar.gz yosys-1827a4896475efae6a88b18bad8787bcea7c6a92.tar.bz2 yosys-1827a4896475efae6a88b18bad8787bcea7c6a92.zip | |
Minor bugfix in submod
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/hierarchy/submod.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 9f312f82d..e9ee4eef9 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -169,6 +169,7 @@ struct SubmodWorker } new_mod->fixup_ports(); + ct.setup_module(new_mod); for (RTLIL::Cell *cell : submod.cells) { RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell); |