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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-18 15:38:28 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-18 15:38:28 -0700 |
| commit | 09411dd996f75dbce22a6f6979b7d61b0dae24f7 (patch) | |
| tree | 99b157eeca6499e1976e90dee180d058a77854f4 /passes | |
| parent | 266c1ae1226656d90ee6416c214ef64fe8b5906f (diff) | |
| download | yosys-09411dd996f75dbce22a6f6979b7d61b0dae24f7.tar.gz yosys-09411dd996f75dbce22a6f6979b7d61b0dae24f7.tar.bz2 yosys-09411dd996f75dbce22a6f6979b7d61b0dae24f7.zip | |
ice40_dsp to accept $__MUL16X16 too
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/pmgen/ice40_dsp.pmg | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index 1f3590d4e..f2b7f2169 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -6,7 +6,7 @@ state <SigSpec> sigA sigB sigY sigS state <Cell*> addAB muxAB match mul - select mul->type.in($mul) + select mul->type.in($mul, $__MUL16X16) select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10 select GetSize(mul->getPort(\Y)) > 10 endmatch |