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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-16 13:38:47 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-16 13:38:47 -0700 |
| commit | 6b51c154c6812f58676402ebbbdbb18d053ca4be (patch) | |
| tree | abc83b857152cd237fd3b64155bdcee2180b5855 /passes/tests/test_cell.cc | |
| parent | 2d5d82e2b6f7d369c0d41b499646a8719ff0bc20 (diff) | |
| parent | 958be89c47ae4f11b5de07bc026bc2202e2ebc97 (diff) | |
| download | yosys-6b51c154c6812f58676402ebbbdbb18d053ca4be.tar.gz yosys-6b51c154c6812f58676402ebbbdbb18d053ca4be.tar.bz2 yosys-6b51c154c6812f58676402ebbbdbb18d053ca4be.zip | |
Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap
Diffstat (limited to 'passes/tests/test_cell.cc')
| -rw-r--r-- | passes/tests/test_cell.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 319669955..88116eeec 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -43,7 +43,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, RTLIL::Cell *cell = module->addCell("\\UUT", cell_type); RTLIL::Wire *wire; - if (cell_type == "$mux" || cell_type == "$pmux") + if (cell_type.in("$mux", "$pmux")) { int width = 1 + xorshift32(8); int swidth = cell_type == "$mux" ? 1 : 1 + xorshift32(8); @@ -264,7 +264,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, cell->setPort("\\Y", wire); } - if (muxdiv && (cell_type == "$div" || cell_type == "$mod")) { + if (muxdiv && cell_type.in("$div", "$mod")) { auto b_not_zero = module->ReduceBool(NEW_ID, cell->getPort("\\B")); auto div_out = module->addWire(NEW_ID, GetSize(cell->getPort("\\Y"))); module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(div_out)), div_out, b_not_zero, cell->getPort("\\Y")); |