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| author | Xiretza <xiretza@xiretza.xyz> | 2020-04-08 19:30:47 +0200 |
|---|---|---|
| committer | Xiretza <xiretza@xiretza.xyz> | 2020-05-28 22:59:03 +0200 |
| commit | 17163cf43a6b6eec9aac44f6a4463dda54b8ed68 (patch) | |
| tree | 02dd1e144c36eb40565cbb792726c7d8d4573eb4 /passes/tests/test_cell.cc | |
| parent | 0d99522b3c2ca2502129110e09f9988874e37abc (diff) | |
| download | yosys-17163cf43a6b6eec9aac44f6a4463dda54b8ed68.tar.gz yosys-17163cf43a6b6eec9aac44f6a4463dda54b8ed68.tar.bz2 yosys-17163cf43a6b6eec9aac44f6a4463dda54b8ed68.zip | |
Add flooring modulo operator
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).
This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
Diffstat (limited to 'passes/tests/test_cell.cc')
| -rw-r--r-- | passes/tests/test_cell.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index cdbe922b2..bc5ff598e 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -264,7 +264,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, cell->setPort(ID::Y, wire); } - if (muxdiv && cell_type.in(ID($div), ID($mod))) { + if (muxdiv && cell_type.in(ID($div), ID($mod), ID($modfloor))) { auto b_not_zero = module->ReduceBool(NEW_ID, cell->getPort(ID::B)); auto div_out = module->addWire(NEW_ID, GetSize(cell->getPort(ID::Y))); module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(div_out)), div_out, b_not_zero, cell->getPort(ID::Y)); @@ -839,6 +839,7 @@ struct TestCellPass : public Pass { cell_types[ID($mul)] = "ABSY"; cell_types[ID($div)] = "ABSY"; cell_types[ID($mod)] = "ABSY"; + cell_types[ID($modfloor)] = "ABSY"; // cell_types[ID($pow)] = "ABsY"; cell_types[ID($logic_not)] = "ASY"; |