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| author | Clifford Wolf <clifford@clifford.at> | 2015-11-05 12:37:43 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-11-05 12:37:43 +0100 |
| commit | f401eeb0cf43f8b0e9431a02b3dd0780dcbceb32 (patch) | |
| tree | 1c3b5cb2b548bd8a6b5e42f2b696b3c969068386 /passes/techmap | |
| parent | ddf3e2dc657da5e441bd9315bf1a86959a07cab9 (diff) | |
| download | yosys-f401eeb0cf43f8b0e9431a02b3dd0780dcbceb32.tar.gz yosys-f401eeb0cf43f8b0e9431a02b3dd0780dcbceb32.tar.bz2 yosys-f401eeb0cf43f8b0e9431a02b3dd0780dcbceb32.zip | |
Bugfix in mapping $tribuf to $_TBUF_
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/simplemap.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 956cd48fe..f6ac3964b 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -293,7 +293,7 @@ void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *gate = module->addCell(NEW_ID, "$_TBUF_"); gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src")); gate->setPort("\\A", sig_a[i]); - gate->setPort("\\E", sig_e[i]); + gate->setPort("\\E", sig_e); gate->setPort("\\Y", sig_y[i]); } } |