diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-31 13:03:03 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-31 13:03:03 -0700 |
| commit | eb08e71bd10004cb37c3ceab37607866d9240630 (patch) | |
| tree | 21754a7525d42c3662d081c7d9b995d731fae00f /passes/techmap | |
| parent | a379234f56753c3d72a6966c380ac6f83fde789c (diff) | |
| parent | ac2aff9e28a087a9a2697cd6ccf754af738903a7 (diff) | |
| download | yosys-eb08e71bd10004cb37c3ceab37607866d9240630.tar.gz yosys-eb08e71bd10004cb37c3ceab37607866d9240630.tar.bz2 yosys-eb08e71bd10004cb37c3ceab37607866d9240630.zip | |
Merge branch 'xaig' into xc7mux
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/abc9.cc | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index f14828745..01842dbf2 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -537,11 +537,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri output_bits.insert({wire, i}); } else { - //if (w->name == "\\__dummy_o__") { - // log("Don't call ABC as there is nothing to map.\n"); - // goto cleanup; - //} - // Attempt another wideports_split here because there // exists the possibility that different bits of a port // could be an input and output, therefore parse_xaiger() @@ -752,7 +747,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri // log("Don't call ABC as there is nothing to map.\n"); //} -cleanup: if (cleanup) { log("Removing temp directory.\n"); |