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| author | Clifford Wolf <clifford@clifford.at> | 2017-02-13 16:55:25 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-02-13 16:55:25 +0100 |
| commit | db7314bc02b4e8b1827993cd844eac9c7070579f (patch) | |
| tree | ef50bf3bffee815d5dfe676ec5934345bce1c76f /passes/techmap | |
| parent | 76c4ee096bba99f787dd042bd9a6e988cf72f2dc (diff) | |
| download | yosys-db7314bc02b4e8b1827993cd844eac9c7070579f.tar.gz yosys-db7314bc02b4e8b1827993cd844eac9c7070579f.tar.bz2 yosys-db7314bc02b4e8b1827993cd844eac9c7070579f.zip | |
Fix techmap for inout ports connected to inout ports
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/techmap.cc | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 6784f48c3..b351d3be8 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -305,10 +305,15 @@ struct TechmapWorker // approach that yields nicer outputs: // replace internal wires that are connected to external wires - if (w->port_output) + if (w->port_output && !w->port_input) { port_signal_map.add(c.second, c.first); - else + } else + if (!w->port_output && w->port_input) { port_signal_map.add(c.first, c.second); + } else { + module->connect(c); + extra_connect = SigSig(); + } for (auto &attr : w->attributes) { if (attr.first == "\\src") |