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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-03 15:05:57 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-03 15:05:57 -0700 |
| commit | d9c4644e88b916d1eadfd401abf297c0995b6462 (patch) | |
| tree | c6355f3671d0399814f5e9257e7f5decdf906b7f /passes/techmap | |
| parent | 67005633e246e47683b11e13f08afb788bc9de02 (diff) | |
| parent | c2e29ab809c5eb3ac89d50868d0e88d831c33d52 (diff) | |
| download | yosys-d9c4644e88b916d1eadfd401abf297c0995b6462.tar.gz yosys-d9c4644e88b916d1eadfd401abf297c0995b6462.tar.bz2 yosys-d9c4644e88b916d1eadfd401abf297c0995b6462.zip | |
Merge remote-tracking branch 'origin/master' into clifford/specify
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/dffinit.cc | 3 | ||||
| -rw-r--r-- | passes/techmap/shregmap.cc | 12 |
2 files changed, 13 insertions, 2 deletions
diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc index 48390488e..0ad33dc0e 100644 --- a/passes/techmap/dffinit.cc +++ b/passes/techmap/dffinit.cc @@ -102,7 +102,8 @@ struct DffinitPass : public Pass { if (wire->attributes.count("\\init")) { Const value = wire->attributes.at("\\init"); for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) - init_bits[sigmap(SigBit(wire, i))] = value[i]; + if (value[i] != State::Sx) + init_bits[sigmap(SigBit(wire, i))] = value[i]; } if (wire->port_output) for (auto bit : sigmap(wire)) diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index a541b33be..75eedfbcc 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -178,7 +178,17 @@ struct ShregmapTechXilinx7 : ShregmapTech // Only map if $shiftx exclusively covers the shift register if (shiftx->type == "$shiftx") { - if (GetSize(taps) != shiftx->getParam("\\A_WIDTH").as_int()) + if (GetSize(taps) > shiftx->getParam("\\A_WIDTH").as_int()) + return false; + // Due to padding the most significant bits of A may be 1'bx, + // and if so, discount them + if (GetSize(taps) < shiftx->getParam("\\A_WIDTH").as_int()) { + const SigSpec A = shiftx->getPort("\\A"); + const int A_width = shiftx->getParam("\\A_WIDTH").as_int(); + for (int i = GetSize(taps); i < A_width; ++i) + if (A[i] != RTLIL::Sx) return false; + } + else if (GetSize(taps) != shiftx->getParam("\\A_WIDTH").as_int()) return false; } else if (shiftx->type == "$mux") { |