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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 17:13:56 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 17:13:56 -0700 |
| commit | d7d5ea6e0cc7cc0db7bb510d3d265dafc7aa93ec (patch) | |
| tree | b84e988f7bbe2fa131275c81189a24e5a556b00a /passes/techmap | |
| parent | 5087d1c2c27c0992c12337565f026573af1c12b4 (diff) | |
| download | yosys-d7d5ea6e0cc7cc0db7bb510d3d265dafc7aa93ec.tar.gz yosys-d7d5ea6e0cc7cc0db7bb510d3d265dafc7aa93ec.tar.bz2 yosys-d7d5ea6e0cc7cc0db7bb510d3d265dafc7aa93ec.zip | |
Remove redundant check (done further down)
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/muxcover.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc index ce9d145d4..b162fae22 100644 --- a/passes/techmap/muxcover.cc +++ b/passes/techmap/muxcover.cc @@ -160,7 +160,7 @@ struct MuxcoverWorker int prepare_decode_mux(SigBit &A, SigBit B, SigBit sel, SigBit bit) { - if (A == B || sel == State::Sx || A == State::Sx || B == State::Sx) + if (A == B || sel == State::Sx) return 0; tuple<SigBit, SigBit, SigBit> key(A, B, sel); |