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| author | whitequark <whitequark@whitequark.org> | 2020-06-03 16:25:46 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-06-04 00:02:12 +0000 |
| commit | d3e21003060a6395089a21ea2f81a7a689eb1884 (patch) | |
| tree | 394c31b0113c6de507bc9d2c21fa9bd888e110bc /passes/techmap | |
| parent | 66255dab4ef3f7257aec65bbbf5b1901f2ee1ebd (diff) | |
| download | yosys-d3e21003060a6395089a21ea2f81a7a689eb1884.tar.gz yosys-d3e21003060a6395089a21ea2f81a7a689eb1884.tar.bz2 yosys-d3e21003060a6395089a21ea2f81a7a689eb1884.zip | |
flatten: simplify. NFC.
Remove redundant sigmaps.
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/flatten.cc | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index 82e697495..75345fcc1 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -52,7 +52,6 @@ void apply_prefix(IdString prefix, RTLIL::SigSpec &sig, RTLIL::Module *module) struct FlattenWorker { dict<std::pair<IdString, dict<IdString, RTLIL::Const>>, RTLIL::Module*> cache; - dict<Module*, SigMap> sigmaps; pool<IdString> flatten_do_list; pool<IdString> flatten_done_list; @@ -122,6 +121,8 @@ struct FlattenWorker design->select(module, w); } + SigMap sigmap(module); + SigMap tpl_sigmap(tpl); pool<SigBit> tpl_written_bits; @@ -185,10 +186,7 @@ struct FlattenWorker // connect internal and external wires - if (sigmaps.count(module) == 0) - sigmaps[module].set(module); - - if (sigmaps.at(module)(c.first).has_const()) + if (sigmap(c.first).has_const()) log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n", log_id(module), log_id(cell), log_id(it.first), log_signal(c.first), log_signal(c.second)); @@ -258,8 +256,6 @@ struct FlattenWorker bool did_something = false; LogMakeDebugHdl mkdebug; - SigMap sigmap(module); - for (auto cell : module->selected_cells()) { if (!design->has(cell->type)) |