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| author | Clifford Wolf <clifford@clifford.at> | 2015-07-18 12:16:27 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-07-18 12:16:27 +0200 |
| commit | ad919ae4e3a86e6726adf8dd66ae5468397c9d27 (patch) | |
| tree | 6497db1e3a834f8d34bfbbfa046b810457784f76 /passes/techmap | |
| parent | 54588a276a0c18c06ed6a4eb98a29b373d4719b5 (diff) | |
| download | yosys-ad919ae4e3a86e6726adf8dd66ae5468397c9d27.tar.gz yosys-ad919ae4e3a86e6726adf8dd66ae5468397c9d27.tar.bz2 yosys-ad919ae4e3a86e6726adf8dd66ae5468397c9d27.zip | |
Fixed techmap processes error msg
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/techmap.cc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 63923a5cf..1fb19fc60 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -159,9 +159,10 @@ struct TechmapWorker void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl) { if (tpl->processes.size() != 0) { - log("Technology map yielded processes:\n"); + log("Technology map yielded processes:"); for (auto &it : tpl->processes) - log(" %s",RTLIL::id2cstr(it.first)); + log(" %s",RTLIL::id2cstr(it.first)); + log("\n"); if (autoproc_mode) { Pass::call_on_module(tpl->design, tpl, "proc"); log_assert(GetSize(tpl->processes) == 0); |