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authorEddie Hung <eddie@fpgeh.com>2020-01-22 10:08:48 -0800
committerEddie Hung <eddie@fpgeh.com>2020-01-22 10:08:48 -0800
commita94b41011d5ec9514739c52b963e0bd96890973f (patch)
tree7f8df26dafcd23e4f13b69ce678a0faa5820951b /passes/techmap
parent3b44b53e946780ac25581f236be7c836fa6927bf (diff)
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abc9: error out if flip-flop init is 1'b1 for '-dff'
Due to ABC sequential synthesis restriction
Diffstat (limited to 'passes/techmap')
-rw-r--r--passes/techmap/abc9.cc2
1 files changed, 2 insertions, 0 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index b0e2c7697..2568a6cd1 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -1069,6 +1069,8 @@ struct Abc9Pass : public Pass {
SigSpec abc9_init = assign_map(abc9_init_wire);
if (!abc9_init.is_fully_const())
log_error("'%s.init' is not a constant wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
+ if (abc9_init == State::S1)
+ log_error("'%s.init' in module '%s' has value 1'b1 which is not supported by 'abc9 -dff'.\n", cell->name.c_str(), log_id(module));
r2 = cell->attributes.insert(std::make_pair(ID(abc9_init), abc9_init.as_const()));
log_assert(r2.second);
}