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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-25 15:34:02 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-25 15:34:02 -0800 |
| commit | 721f6a14fb632b671ba10ed13cafad1263e2b073 (patch) | |
| tree | 71c940fbf95a5f15be3489043a42dfe3424cf287 /passes/techmap | |
| parent | 0ca3fd6a1cca6f12db4069ed6f73b814aee2eeaf (diff) | |
| download | yosys-721f6a14fb632b671ba10ed13cafad1263e2b073.tar.gz yosys-721f6a14fb632b671ba10ed13cafad1263e2b073.tar.bz2 yosys-721f6a14fb632b671ba10ed13cafad1263e2b073.zip | |
read_aiger to accept empty string for clk_name, passable only if no latches
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/abc9.cc | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 90234ea33..68e54f518 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -523,8 +523,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri bool builtin_lib = liberty_file.empty(); RTLIL::Design *mapped_design = new RTLIL::Design; //parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode); - buffer = stringf("%s/%s", tempdir_name.c_str(), "input.symbols"); - AigerReader reader(mapped_design, ifs, "\\netlist", "\\clk", buffer, true /* wideports */); + AigerReader reader(mapped_design, ifs, "\\netlist", "" /* clk_name */, "" /* map_filename */, true /* wideports */); reader.parse_xaiger(); ifs.close(); |