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| author | whitequark <whitequark@whitequark.org> | 2021-01-29 02:55:51 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-01-29 02:55:51 +0000 |
| commit | 708eb327a1e88f726b8d426dba35abc29339a634 (patch) | |
| tree | 950cdb788f08318b204180cdc2c58f21dc4b1467 /passes/techmap | |
| parent | ffa1cb836be07b2bfec46da76ef7c7ab5fda6995 (diff) | |
| parent | 2364820f504beef06d0d94d6b2e82eddffeb57c1 (diff) | |
| download | yosys-708eb327a1e88f726b8d426dba35abc29339a634.tar.gz yosys-708eb327a1e88f726b8d426dba35abc29339a634.tar.bz2 yosys-708eb327a1e88f726b8d426dba35abc29339a634.zip | |
Merge pull request #2564 from whitequark/flatten-improve-error
flatten: clarify confusing error message
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/flatten.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index ec5f83fb0..f35b7ff60 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -211,7 +211,7 @@ struct FlattenWorker log_assert(new_conn.first.size() == new_conn.second.size()); if (sigmap(new_conn.first).has_const()) - log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n", + log_error("Cell port %s.%s.%s is driving constant bits: %s <= %s\n", log_id(module), log_id(cell), log_id(port_it.first), log_signal(new_conn.first), log_signal(new_conn.second)); module->connect(new_conn); |