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author | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2019-02-24 22:08:52 -0800 |
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committer | Clifford Wolf <clifford@clifford.at> | 2019-02-26 09:39:46 -0800 |
commit | 61fc411c5d7237e420ee6eb9f6eb093e70d1007d (patch) | |
tree | 52cab3b364be7ac5d98ef467a545ad651c02570b /passes/techmap | |
parent | c258b99040c8414952a3aceae874dc47563540dc (diff) | |
download | yosys-61fc411c5d7237e420ee6eb9f6eb093e70d1007d.tar.gz yosys-61fc411c5d7237e420ee6eb9f6eb093e70d1007d.tar.bz2 yosys-61fc411c5d7237e420ee6eb9f6eb093e70d1007d.zip |
Clean up some whitepsace outliers
Diffstat (limited to 'passes/techmap')
-rw-r--r-- | passes/techmap/dfflibmap.cc | 4 | ||||
-rw-r--r-- | passes/techmap/flowmap.cc | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index b0528d473..274177a68 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -660,8 +660,8 @@ struct DfflibmapPass : public Pass { map_adff_to_dff("$_DFF_PP0_", "$_DFF_P_"); map_adff_to_dff("$_DFF_PP1_", "$_DFF_P_"); - log(" final dff cell mappings:\n"); - logmap_all(); + log(" final dff cell mappings:\n"); + logmap_all(); for (auto &it : design->modules_) if (design->selected(it.second) && !it.second->get_bool_attribute("\\blackbox")) diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc index ddbd7bf5d..0b7931e48 100644 --- a/passes/techmap/flowmap.cc +++ b/passes/techmap/flowmap.cc @@ -132,9 +132,9 @@ static void dump_dot_graph(string filename, pool<RTLIL::SigBit> nodes, dict<RTLIL::SigBit, pool<RTLIL::SigBit>> edges, pool<RTLIL::SigBit> inputs, pool<RTLIL::SigBit> outputs, std::function<GraphStyle(RTLIL::SigBit)> node_style = - [](RTLIL::SigBit) { return GraphStyle{}; }, + [](RTLIL::SigBit) { return GraphStyle{}; }, std::function<GraphStyle(RTLIL::SigBit, RTLIL::SigBit)> edge_style = - [](RTLIL::SigBit, RTLIL::SigBit) { return GraphStyle{}; }, + [](RTLIL::SigBit, RTLIL::SigBit) { return GraphStyle{}; }, string name = "") { FILE *f = fopen(filename.c_str(), "w"); |