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author | Clifford Wolf <clifford@clifford.at> | 2013-11-24 17:17:21 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-11-24 17:17:21 +0100 |
commit | 609caa23b5e12547c043dc4a1827d1a531af1992 (patch) | |
tree | 297e7d5b77b28eebccc3bd8e7af318f174165744 /passes/techmap | |
parent | 1e6836933d8b74d391f816ccdcf71c972f8b1db1 (diff) | |
download | yosys-609caa23b5e12547c043dc4a1827d1a531af1992.tar.gz yosys-609caa23b5e12547c043dc4a1827d1a531af1992.tar.bz2 yosys-609caa23b5e12547c043dc4a1827d1a531af1992.zip |
Implemented correct handling of signed module parameters
Diffstat (limited to 'passes/techmap')
-rw-r--r-- | passes/techmap/techmap.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 4f9d9c4e4..c3af697be 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -239,7 +239,7 @@ static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL:: tpl = techmap_cache[key]; } else { if (cell->parameters.size() != 0) { - derived_name = tpl->derive(map, parameters); + derived_name = tpl->derive(map, parameters, cell->signed_parameters); tpl = map->modules[derived_name]; log_continue = true; } |