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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-07 16:57:32 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-07 16:57:32 -0700 |
| commit | 5a46a0b38584014c3644cc434458638874bd4d75 (patch) | |
| tree | 4b4324c642b39232c2fecafdfc278d73f8a6a82b /passes/techmap | |
| parent | 1e201a9b010badec6f220476dc6bc03a06de5b69 (diff) | |
| download | yosys-5a46a0b38584014c3644cc434458638874bd4d75.tar.gz yosys-5a46a0b38584014c3644cc434458638874bd4d75.tar.bz2 yosys-5a46a0b38584014c3644cc434458638874bd4d75.zip | |
Fine tune aigerparse
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/abc9.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 06a638558..af9439e41 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -586,7 +586,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri RTLIL::Cell *cell; RTLIL::SigBit a_bit = c->getPort("\\A").as_bit(); RTLIL::SigBit y_bit = c->getPort("\\Y").as_bit(); - if (!lut_costs.empty() || !lut_file.empty()) { + if (!a_bit.wire) { + c->setPort("\\Y", module->addWire(NEW_ID)); + module->connect(module->wires_[remap_name(y_bit.wire->name)], RTLIL::S1); + } + else if (!lut_costs.empty() || !lut_file.empty()) { RTLIL::Cell* driving_lut = nullptr; // ABC can return NOT gates that drive POs if (!a_bit.wire->port_input) { |