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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-04-14 15:44:17 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-04-15 08:11:15 +0200 |
| commit | 4c52691a58a469a525401bbc83c65f262b2a5504 (patch) | |
| tree | 562000c89f77a5517fe5702a3b1be1325c04a9b7 /passes/techmap | |
| parent | a143f04e7d665fa38e5b69effd66f1e56e338544 (diff) | |
| download | yosys-4c52691a58a469a525401bbc83c65f262b2a5504.tar.gz yosys-4c52691a58a469a525401bbc83c65f262b2a5504.tar.bz2 yosys-4c52691a58a469a525401bbc83c65f262b2a5504.zip | |
abc9_ops: Add a check ensuring that connected port actually exists.
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 00af36615..8ae1b51ff 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -434,6 +434,9 @@ void prep_delays(RTLIL::Design *design, bool dff_mode) auto &t = timing.at(derived_type).required; for (auto &conn : cell->connections_) { auto port_wire = inst_module->wire(conn.first); + if (!port_wire) + log_error("Port %s in cell %s (type %s) of module %s does not actually exist", + log_id(conn.first), log_id(cell->name), log_id(cell->type), log_id(module->name)); if (!port_wire->port_input) continue; |