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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-30 15:50:47 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-30 15:50:47 -0700 |
| commit | 4a6b9af227cb22e89fd463c665016544060d2acd (patch) | |
| tree | 07dc37a76516726d7432e07efc6ec7a4c659254e /passes/techmap | |
| parent | 1ad33c3b5ac91fc4e6cb6e2ff4b606a693838c2b (diff) | |
| download | yosys-4a6b9af227cb22e89fd463c665016544060d2acd.tar.gz yosys-4a6b9af227cb22e89fd463c665016544060d2acd.tar.bz2 yosys-4a6b9af227cb22e89fd463c665016544060d2acd.zip | |
Fix spelling
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/abc9.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 82f149c8c..4bda388de 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -924,7 +924,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri else { // Attempt another wideports_split here because there // exists the possibility that different bits of a port - // could be an input and output, therefore parse_xiager() + // could be an input and output, therefore parse_xaiger() // could not combine it into a wideport auto r = wideports_split(w->name.str()); wire = module->wire(r.first); |