ecp5: Adding synchronous set/reset support

Signed-off-by: David Shah <davey1576@gmail.com>

3 files changed, 155 insertions, 3 deletions

diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc
index 140a9f892..4faa0ab00 100644
--- a/passes/techmap/Makefile.inc
+++ b/passes/techmap/Makefile.inc
@@ -35,6 +35,7 @@ OBJS += passes/techmap/insbuf.o
 OBJS += passes/techmap/attrmvcp.o
 OBJS += passes/techmap/attrmap.o
 OBJS += passes/techmap/zinit.o
+OBJS += passes/techmap/dff2dffs.o
 endif
 
 GENFILES += passes/techmap/techmap.inc
@@ -57,4 +58,3 @@ yosys-filterlib$(EXE): passes/techmap/filterlib.o
 	$(Q) mkdir -p $(dir $@)
 	$(P) $(LD) -o yosys-filterlib$(EXE) $(LDFLAGS) $^ $(LDLIBS)
 endif
-
diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc
index 1b8920bb7..4d515f174 100644
--- a/passes/techmap/dff2dffe.cc
+++ b/passes/techmap/dff2dffe.cc
@@ -279,8 +279,9 @@ struct Dff2dffePass : public Pass {
 		log("    -direct-match <pattern>\n");
 		log("        like -direct for all DFF cell types matching the expression.\n");
 		log("        this will use $__DFFE_* as <external_gate_type> matching the\n");
-		log("        internal gate type $_DFF_*_, except for $_DFF_[NP]_, which is\n");
-		log("        converted to $_DFFE_[NP]_.\n");
+		log("        internal gate type $_DFF_*_, and $__DFFSE_* for those matching\n");
+		log("        $_DFFS_*_, except for $_DFF_[NP]_, which is converted to \n");
+		log("        $_DFFE_[NP]_.\n");
 		log("\n");
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
@@ -315,6 +316,15 @@ struct Dff2dffePass : public Pass {
 				if (patmatch(pattern, "$_DFF_PN1_")) found_match = true, direct_dict["$_DFF_PN1_"] = "$__DFFE_PN1";
 				if (patmatch(pattern, "$_DFF_PP0_")) found_match = true, direct_dict["$_DFF_PP0_"] = "$__DFFE_PP0";
 				if (patmatch(pattern, "$_DFF_PP1_")) found_match = true, direct_dict["$_DFF_PP1_"] = "$__DFFE_PP1";
+
+				if (patmatch(pattern, "$__DFFS_NN0_")) found_match = true, direct_dict["$__DFFS_NN0_"] = "$__DFFSE_NN0";
+				if (patmatch(pattern, "$__DFFS_NN1_")) found_match = true, direct_dict["$__DFFS_NN1_"] = "$__DFFSE_NN1";
+				if (patmatch(pattern, "$__DFFS_NP0_")) found_match = true, direct_dict["$__DFFS_NP0_"] = "$__DFFSE_NP0";
+				if (patmatch(pattern, "$__DFFS_NP1_")) found_match = true, direct_dict["$__DFFS_NP1_"] = "$__DFFSE_NP1";
+				if (patmatch(pattern, "$__DFFS_PN0_")) found_match = true, direct_dict["$__DFFS_PN0_"] = "$__DFFSE_PN0";
+				if (patmatch(pattern, "$__DFFS_PN1_")) found_match = true, direct_dict["$__DFFS_PN1_"] = "$__DFFSE_PN1";
+				if (patmatch(pattern, "$__DFFS_PP0_")) found_match = true, direct_dict["$__DFFS_PP0_"] = "$__DFFSE_PP0";
+				if (patmatch(pattern, "$__DFFS_PP1_")) found_match = true, direct_dict["$__DFFS_PP1_"] = "$__DFFSE_PP1";
 				if (!found_match)
 					log_cmd_error("No cell types matched pattern '%s'.\n", pattern);
 				continue;
diff --git a/passes/techmap/dff2dffs.cc b/passes/techmap/dff2dffs.cc
new file mode 100644
index 000000000..0bfbdc965
--- /dev/null
+++ b/passes/techmap/dff2dffs.cc
@@ -0,0 +1,142 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  David Shah <dave@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct Dff2dffsPass : public Pass {
+	Dff2dffsPass() : Pass("dff2dffs", "process sync set/reset with SR over CE priority") { }
+	virtual void help()
+	{
+		log("\n");
+		log("    dff2dffs [options] [selection]\n");
+		log("\n");
+		log("Merge synchronous set/reset $_MUX_ cells to create $__DFFS_[NP][NP][01], to be run before\n");
+		log("dff2dffe for SR over CE priority.\n");
+		log("\n");
+	}
+	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	{
+		log_header(design, "Executing dff2dffs pass (merge synchronous set/reset into FF cells).\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			// if (args[argidx] == "-singleton") {
+			// 	singleton_mode = true;
+			// 	continue;
+			// }
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		pool<IdString> dff_types;
+		dff_types.insert("$_DFF_N_");
+		dff_types.insert("$_DFF_P_");
+
+		for (auto module : design->selected_modules())
+		{
+			log("Merging set/reset $_MUX_ cells into DFFs in %s.\n", log_id(module));
+
+			SigMap sigmap(module);
+			dict<SigBit, Cell*> sr_muxes;
+			vector<Cell*> ff_cells;
+
+			for (auto cell : module->selected_cells())
+			{
+				if (dff_types.count(cell->type)) {
+					ff_cells.push_back(cell);
+					continue;
+				}
+
+				if (cell->type != "$_MUX_")
+					continue;
+
+				SigBit bit_a = sigmap(cell->getPort("\\A"));
+				SigBit bit_b = sigmap(cell->getPort("\\B"));
+
+				if (bit_a.wire == nullptr || bit_b.wire == nullptr)
+					sr_muxes[sigmap(cell->getPort("\\Y"))] = cell;
+			}
+
+			for (auto cell : ff_cells)
+			{
+				SigSpec sig_d = cell->getPort("\\D");
+
+				if (GetSize(sig_d) < 1)
+					continue;
+
+				SigBit bit_d = sigmap(sig_d[0]);
+
+				if (sr_muxes.count(bit_d) == 0)
+					continue;
+
+				Cell *mux_cell = sr_muxes.at(bit_d);
+				SigBit bit_a = sigmap(mux_cell->getPort("\\A"));
+				SigBit bit_b = sigmap(mux_cell->getPort("\\B"));
+				SigBit bit_s = sigmap(mux_cell->getPort("\\S"));
+
+				log("  Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell),
+						log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type));
+
+				SigBit sr_val, sr_sig;
+				bool invert_sr;
+				sr_sig = bit_s;
+				if (bit_a.wire == nullptr) {
+					bit_d = bit_b;
+					sr_val = bit_a;
+					invert_sr = true;
+				} else {
+					log_assert(bit_b.wire == nullptr);
+					bit_d = bit_a;
+					sr_val = bit_b;
+					invert_sr = false;
+				}
+
+				if (sr_val == State::S1) {
+					if (cell->type == "$_DFF_N_") {
+						if (invert_sr) cell->type = "$__DFFS_NN1_";
+						else cell->type = "$__DFFS_NP1_";
+					} else {
+						log_assert(cell->type == "$_DFF_P_");
+						if (invert_sr) cell->type = "$__DFFS_PN1_";
+						else cell->type = "$__DFFS_PP1_";
+					}
+				} else {
+					if (cell->type == "$_DFF_N_") {
+						if (invert_sr) cell->type = "$__DFFS_NN0_";
+						else cell->type = "$__DFFS_NP0_";
+					} else {
+						log_assert(cell->type == "$_DFF_P_");
+						if (invert_sr) cell->type = "$__DFFS_PN0_";
+						else cell->type = "$__DFFS_PP0_";
+					}
+				}
+				cell->setPort("\\R", sr_sig);
+				cell->setPort("\\D", bit_d);
+			}
+		}
+	}
+} Dff2dffsPass;
+
+PRIVATE_NAMESPACE_END