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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-11 16:25:59 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-11 16:25:59 -0700 |
| commit | 3c1f1a6605a4463117ba358fc9528c4999628b81 (patch) | |
| tree | 20e56cfd4d5d1761b97b924934f458858e9384d2 /passes/techmap | |
| parent | f587950bde58b326e1f7319c84d5652a0dc43216 (diff) | |
| download | yosys-3c1f1a6605a4463117ba358fc9528c4999628b81.tar.gz yosys-3c1f1a6605a4463117ba358fc9528c4999628b81.tar.bz2 yosys-3c1f1a6605a4463117ba358fc9528c4999628b81.zip | |
Fix ordering of when to insert zero index
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/pmux2shiftx.cc | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/passes/techmap/pmux2shiftx.cc b/passes/techmap/pmux2shiftx.cc index f8cdf5783..6ffc27a4c 100644 --- a/passes/techmap/pmux2shiftx.cc +++ b/passes/techmap/pmux2shiftx.cc @@ -65,8 +65,7 @@ struct Pmux2ShiftxPass : public Pass { const int clog2width = ceil(log2(s_width)); RTLIL::SigSpec pmux_b; - pmux_b.append(RTLIL::Const(0, clog2width)); - for (int i = s_width-1; i > 0; i--) + for (int i = s_width-1; i >= 0; i--) pmux_b.append(RTLIL::Const(i, clog2width)); shiftx_a.append(cell->getPort("\\B")); pmux_s.append(cell->getPort("\\S")); |