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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-25 23:01:42 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-25 23:01:42 +0100 |
| commit | 331f8b8d0ba2c11aac89f15622b23a0284c538d7 (patch) | |
| tree | 0a764eb3eb3824819760511eb66fd963afd5b34a /passes/techmap | |
| parent | 9ae21263f0de0c0011c7de290af3600ddeb51a34 (diff) | |
| download | yosys-331f8b8d0ba2c11aac89f15622b23a0284c538d7.tar.gz yosys-331f8b8d0ba2c11aac89f15622b23a0284c538d7.tar.bz2 yosys-331f8b8d0ba2c11aac89f15622b23a0284c538d7.zip | |
Bugfix in iopadmap
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/iopadmap.cc | 13 |
1 files changed, 3 insertions, 10 deletions
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index 75d02c828..3fba0e618 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -114,18 +114,11 @@ struct IopadmapPass : public Pass { } extra_args(args, argidx, design); - for (auto &it : design->modules_) + for (auto module : design->selected_modules()) { - RTLIL::Module *module = it.second; - - if (!design->selected(module) || module->get_bool_attribute("\\blackbox")) - continue; - - for (auto &it2 : module->wires_) + for (auto wire : module->selected_wires()) { - RTLIL::Wire *wire = it2.second; - - if (!wire->port_id || !design->selected(module, wire)) + if (!wire->port_id) continue; std::string celltype, portname, portname2; |