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| author | Clifford Wolf <clifford@clifford.at> | 2019-08-17 15:07:16 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-17 15:07:16 +0200 |
| commit | 2a78a1fd00fe66972885117efb1ac6a8b095f061 (patch) | |
| tree | 552cff1002a6941b56b7c3a3df5022d6ed049846 /passes/techmap | |
| parent | ae5d8dc939678c85ba6dea78fdcfa133ddea0b92 (diff) | |
| parent | 27d59dc0550432458d4bd636081a7b9f4b4411fe (diff) | |
| download | yosys-2a78a1fd00fe66972885117efb1ac6a8b095f061.tar.gz yosys-2a78a1fd00fe66972885117efb1ac6a8b095f061.tar.bz2 yosys-2a78a1fd00fe66972885117efb1ac6a8b095f061.zip | |
Merge pull request #1283 from YosysHQ/clifford/fix1255
Fix various NDEBUG compiler warnings
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/abc9.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index dac0f3a75..c1d4fff2d 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -739,7 +739,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri for (auto driver_cell : bit_drivers.at(it.first)) for (auto user_cell : it.second) toposort.edge(driver_cell, user_cell); - bool no_loops = toposort.sort(); + bool no_loops YS_ATTRIBUTE(unused) = toposort.sort(); log_assert(no_loops); for (auto ii = toposort.sorted.rbegin(); ii != toposort.sorted.rend(); ii++) { |