diff options
| author | clairexen <claire@symbioticeda.com> | 2020-08-20 16:18:40 +0200 | 
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-08-20 16:18:40 +0200 | 
| commit | 1cdb533fa58c8dbb6f8e45665a89134f5184ed40 (patch) | |
| tree | 825e87a29bfdf713499921288cfe6fe8c8e4080f /passes/techmap | |
| parent | 23719ad46dd13e338851961565858e25c66d63f7 (diff) | |
| parent | 522788f0165899b5b73f12ee283b4c135fb86792 (diff) | |
| download | yosys-1cdb533fa58c8dbb6f8e45665a89134f5184ed40.tar.gz yosys-1cdb533fa58c8dbb6f8e45665a89134f5184ed40.tar.bz2 yosys-1cdb533fa58c8dbb6f8e45665a89134f5184ed40.zip  | |
Merge pull request #2319 from YosysHQ/mwk/techmap-celltype-pattern
techmap: Add support for [] wildcards in techmap_celltype.
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/techmap.cc | 36 | 
1 files changed, 32 insertions, 4 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index c22ae8ef0..e8085595b 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -1007,7 +1007,9 @@ struct TechmapPass : public Pass {  		log("\n");  		log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");  		log("match cells with a type that match the text value of this attribute. Otherwise\n"); -		log("the module name will be used to match the cell.\n"); +		log("the module name will be used to match the cell.  Multiple space-separated cell\n"); +		log("types can be listed, and wildcards using [] will be expanded (ie. \"$_DFF_[PN]_\"\n"); +		log("is the same as \"$_DFF_P_ $_DFF_N_\").\n");  		log("\n");  		log("When a module in the map file has the 'techmap_simplemap' attribute set, techmap\n");  		log("will use 'simplemap' (see 'help simplemap') to map cells matching the module.\n"); @@ -1199,8 +1201,27 @@ struct TechmapPass : public Pass {  		for (auto module : map->modules()) {  			if (module->attributes.count(ID::techmap_celltype) && !module->attributes.at(ID::techmap_celltype).bits.empty()) {  				char *p = strdup(module->attributes.at(ID::techmap_celltype).decode_string().c_str()); -				for (char *q = strtok(p, " \t\r\n"); q; q = strtok(nullptr, " \t\r\n")) -					celltypeMap[RTLIL::escape_id(q)].insert(module->name); +				for (char *q = strtok(p, " \t\r\n"); q; q = strtok(nullptr, " \t\r\n")) { +					std::vector<std::string> queue; +					queue.push_back(q); +					while (!queue.empty()) { +						std::string name = queue.back(); +						queue.pop_back(); +						auto pos = name.find('['); +						if (pos == std::string::npos) { +							// No further expansion. +							celltypeMap[RTLIL::escape_id(name)].insert(module->name); +						} else { +							// Expand [] in this name. +							auto epos = name.find(']', pos); +							if (epos == std::string::npos) +								log_error("Malformed techmap_celltype pattern %s\n", q); +							for (size_t i = pos + 1; i < epos; i++) { +								queue.push_back(name.substr(0, pos) + name[i] + name.substr(epos + 1, std::string::npos)); +							} +						} +					} +				}  				free(p);  			} else {  				IdString module_name = module->name.begins_with("\\$") ? @@ -1208,8 +1229,15 @@ struct TechmapPass : public Pass {  				celltypeMap[module_name].insert(module->name);  			}  		} -		for (auto &i : celltypeMap) +		log_debug("Cell type mappings to use:\n"); +		for (auto &i : celltypeMap) {  			i.second.sort(RTLIL::sort_by_id_str()); +			std::string maps = ""; +			for (auto &map : i.second) +				maps += stringf(" %s", log_id(map)); +			log_debug("    %s:%s\n", log_id(i.first), maps.c_str()); +		} +		log_debug("\n");  		for (auto module : design->modules())  			worker.module_queue.insert(module);  | 
