diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 10:00:57 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 10:00:57 -0700 |
| commit | 14e870d4c47e18abf45f82f2d9329d1488e0650c (patch) | |
| tree | 1a0905d2200a45b5e3757a8d6a6d5a26b85419e0 /passes/techmap | |
| parent | 4be417f6e15ee3f3d8da8cd75d8405b90d5b32ba (diff) | |
| download | yosys-14e870d4c47e18abf45f82f2d9329d1488e0650c.tar.gz yosys-14e870d4c47e18abf45f82f2d9329d1488e0650c.tar.bz2 yosys-14e870d4c47e18abf45f82f2d9329d1488e0650c.zip | |
More write_xaiger cleanup
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/abc9.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 47e87fa46..b0c6b6d7b 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -425,7 +425,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri handle_loops(design); - Pass::call(design, stringf("write_xaiger -O -map %s/input.sym %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str())); + Pass::call(design, stringf("write_xaiger -map %s/input.sym %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str())); #if 0 std::string buffer = stringf("%s/%s", tempdir_name.c_str(), "input.xaig"); |