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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-30 11:32:14 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-30 11:32:14 -0700 |
| commit | 0800846e73b6502cfaa2000ea433faa5f1f75a3a (patch) | |
| tree | 134358c675cbc8274d6555ba54453b29e516133d /passes/techmap | |
| parent | fdfc18be91123e2939f134dafc12e1e0c1a82f7b (diff) | |
| download | yosys-0800846e73b6502cfaa2000ea433faa5f1f75a3a.tar.gz yosys-0800846e73b6502cfaa2000ea433faa5f1f75a3a.tar.bz2 yosys-0800846e73b6502cfaa2000ea433faa5f1f75a3a.zip | |
Do not double count LUT1s
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/abc9.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 8966b5c27..b1bd167a4 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -670,7 +670,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset), driver_lut); } - cell_stats["$lut"]++; } else { cell = module->addCell(remap_name(c->name), "$_NOT_"); |