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author | Johann Glaser <Johann.Glaser@gmx.at> | 2013-03-17 22:02:30 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-03-18 07:28:31 +0100 |
commit | cd8008bda01091b7da63d4a2c7b2fe3749ee9f36 (patch) | |
tree | 8da22fcbe26dcad0c0babcba07a965ef0623233b /passes/techmap/techmap.cc | |
parent | ba3793b6420f2a0288c43be0cd4016fd5473acaf (diff) | |
download | yosys-cd8008bda01091b7da63d4a2c7b2fe3749ee9f36.tar.gz yosys-cd8008bda01091b7da63d4a2c7b2fe3749ee9f36.tar.bz2 yosys-cd8008bda01091b7da63d4a2c7b2fe3749ee9f36.zip |
fixed typos
Diffstat (limited to 'passes/techmap/techmap.cc')
-rw-r--r-- | passes/techmap/techmap.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index c05a96cd4..5fd5858aa 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -172,14 +172,14 @@ struct TechmapPass : public Pass { log("\n"); log(" techmap [-map filename] [selection]\n"); log("\n"); - log("This pass implements a very simple technology mapper than replaces cells in\n"); + log("This pass implements a very simple technology mapper that replaces cells in\n"); log("the design with implementations given in form of a verilog or ilang source\n"); log("file.\n"); log("\n"); log(" -map filename\n"); log(" the library of cell implementations to be used.\n"); log(" without this parameter a builtin library is used that\n"); - log(" transform the internal RTL cells to the internal gate\n"); + log(" transforms the internal RTL cells to the internal gate\n"); log(" library.\n"); log("\n"); log("See 'help extract' for a pass that does the opposite thing.\n"); |