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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-10-02 00:42:36 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-10-02 03:24:57 +0200 |
| commit | f9aad606ca9c8f875ce3c3091daf465b73d3f513 (patch) | |
| tree | b33752b61bef503c930f5d0b1227b9d7286870a6 /passes/techmap/simplemap.h | |
| parent | 62739f7bf7b82afccd10c22bdabf89d305485966 (diff) | |
| download | yosys-f9aad606ca9c8f875ce3c3091daf465b73d3f513.tar.gz yosys-f9aad606ca9c8f875ce3c3091daf465b73d3f513.tar.bz2 yosys-f9aad606ca9c8f875ce3c3091daf465b73d3f513.zip | |
simplemap: refactor to use FfData.
Diffstat (limited to 'passes/techmap/simplemap.h')
| -rw-r--r-- | passes/techmap/simplemap.h | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/passes/techmap/simplemap.h b/passes/techmap/simplemap.h index 03a8fb36f..c7654f68c 100644 --- a/passes/techmap/simplemap.h +++ b/passes/techmap/simplemap.h @@ -34,12 +34,7 @@ extern void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell); extern void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell); extern void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell); extern void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell); -extern void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell); -extern void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell); -extern void simplemap_dffe(RTLIL::Module *module, RTLIL::Cell *cell); -extern void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell); -extern void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell); -extern void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell); +extern void simplemap_ff(RTLIL::Module *module, RTLIL::Cell *cell); extern void simplemap(RTLIL::Module *module, RTLIL::Cell *cell); extern void simplemap_get_mappers(dict<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers); |