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| author | Clifford Wolf <clifford@clifford.at> | 2015-04-27 10:16:07 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-04-27 10:16:07 +0200 |
| commit | 794d22969dae1a31af36719574351cf75e4fe033 (patch) | |
| tree | e779b534c6ececb285d55886c67601dacbde7aa4 /passes/techmap/simplemap.h | |
| parent | 8d4a675f91b67d6ce87cb2af19526410cf4c6d36 (diff) | |
| download | yosys-794d22969dae1a31af36719574351cf75e4fe033.tar.gz yosys-794d22969dae1a31af36719574351cf75e4fe033.tar.bz2 yosys-794d22969dae1a31af36719574351cf75e4fe033.zip | |
Added simplemap $lut support
Diffstat (limited to 'passes/techmap/simplemap.h')
| -rw-r--r-- | passes/techmap/simplemap.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/passes/techmap/simplemap.h b/passes/techmap/simplemap.h index dc2a395d3..67be4efef 100644 --- a/passes/techmap/simplemap.h +++ b/passes/techmap/simplemap.h @@ -31,6 +31,7 @@ extern void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell); extern void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell); extern void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell); extern void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell); +extern void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell); extern void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell); extern void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell); extern void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell); |