diff options
| author | Jannis Harder <me@jix.one> | 2022-11-02 17:12:51 +0100 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2022-11-30 18:24:35 +0100 |
| commit | 7203ba7bc1d83777bd2c2c347d45209d8e3d4b84 (patch) | |
| tree | da57415b2168bf02cb0efa485a91769850e66cf8 /passes/techmap/simplemap.h | |
| parent | f2c531e65f4518abe58d04e53d0116583651ac50 (diff) | |
| download | yosys-7203ba7bc1d83777bd2c2c347d45209d8e3d4b84.tar.gz yosys-7203ba7bc1d83777bd2c2c347d45209d8e3d4b84.tar.bz2 yosys-7203ba7bc1d83777bd2c2c347d45209d8e3d4b84.zip | |
Add bitwise `$bweqx` and `$bwmux` cells
The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`)
cells enable compact encoding and decoding of 3-valued logic signals
using multiple 2-valued signals.
Diffstat (limited to 'passes/techmap/simplemap.h')
| -rw-r--r-- | passes/techmap/simplemap.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/passes/techmap/simplemap.h b/passes/techmap/simplemap.h index c7654f68c..30cc1ccfe 100644 --- a/passes/techmap/simplemap.h +++ b/passes/techmap/simplemap.h @@ -31,6 +31,7 @@ extern void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell); extern void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell); extern void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell); extern void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell); +extern void simplemap_bwmux(RTLIL::Module *module, RTLIL::Cell *cell); extern void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell); extern void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell); extern void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell); |