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| author | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-04-14 17:50:23 +0000 |
|---|---|---|
| committer | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-05-14 20:06:53 +0000 |
| commit | 437f3fb342f91d0c1a1a923c92312301a03cb07d (patch) | |
| tree | 9e62ce204f6c05d20a892c8be3eac472ae38ab79 /passes/techmap/simplemap.h | |
| parent | 99b586b28367e1aea8c9e75a8132079c4a3687f9 (diff) | |
| download | yosys-437f3fb342f91d0c1a1a923c92312301a03cb07d.tar.gz yosys-437f3fb342f91d0c1a1a923c92312301a03cb07d.tar.bz2 yosys-437f3fb342f91d0c1a1a923c92312301a03cb07d.zip | |
Replace `std::map` with `dict` for `simplemap_mappers`.
Diffstat (limited to 'passes/techmap/simplemap.h')
| -rw-r--r-- | passes/techmap/simplemap.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/simplemap.h b/passes/techmap/simplemap.h index c2d73ea79..5091050a1 100644 --- a/passes/techmap/simplemap.h +++ b/passes/techmap/simplemap.h @@ -42,7 +42,7 @@ extern void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell); extern void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell); extern void simplemap(RTLIL::Module *module, RTLIL::Cell *cell); -extern void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers); +extern void simplemap_get_mappers(dict<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers); YOSYS_NAMESPACE_END |