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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-22 19:07:55 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-22 19:07:55 -0700 |
| commit | ab11f2aa701f4ff7a8df98d2a4158ea1f661a205 (patch) | |
| tree | d2c8e2b82b7cca57127bd9dd54d3eb40386a88f7 /passes/techmap/simplemap.cc | |
| parent | d90c1e952256dc00d070863835e061d73e4bc6b3 (diff) | |
| parent | 7311be4028a9caad5a0fac1a3433220b4233ef84 (diff) | |
| download | yosys-ab11f2aa701f4ff7a8df98d2a4158ea1f661a205.tar.gz yosys-ab11f2aa701f4ff7a8df98d2a4158ea1f661a205.tar.bz2 yosys-ab11f2aa701f4ff7a8df98d2a4158ea1f661a205.zip | |
Merge https://github.com/cliffordwolf/yosys
Diffstat (limited to 'passes/techmap/simplemap.cc')
| -rw-r--r-- | passes/techmap/simplemap.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index f6ac3964b..777e80142 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -543,7 +543,7 @@ struct SimplemapPass : public Pass { } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { - log_header("Executing SIMPLEMAP pass (map simple cells to gate primitives).\n"); + log_header(design, "Executing SIMPLEMAP pass (map simple cells to gate primitives).\n"); extra_args(args, 1, design); std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers; |