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author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-10-06 22:16:55 +0200 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-10-07 04:24:06 +0200 |
commit | 4e70c3077562e511d6f840c91dd30ade87d66517 (patch) | |
tree | e03d632836952baf936c715927f2d6c8a9691e28 /passes/techmap/simplemap.cc | |
parent | 356ec7bb3980f77d737d9fa6e24e2f0b2159e741 (diff) | |
download | yosys-4e70c3077562e511d6f840c91dd30ade87d66517.tar.gz yosys-4e70c3077562e511d6f840c91dd30ade87d66517.tar.bz2 yosys-4e70c3077562e511d6f840c91dd30ade87d66517.zip |
FfData: some refactoring.
- FfData now keeps track of the module and underlying cell, if any (so
calling emit on FfData created from a cell will replace the existing cell)
- FfData implementation is split off to its own .cc file for faster
compilation
- the "flip FF data sense by inserting inverters in front and after"
functionality that zinit uses is moved onto FfData class and beefed up
to have dffsr support, to support more use cases
Diffstat (limited to 'passes/techmap/simplemap.cc')
-rw-r--r-- | passes/techmap/simplemap.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 04d7ec874..68f44cf6d 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -368,13 +368,13 @@ void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell) module->connect(RTLIL::SigSig(sig_y, sig_ab)); } -void simplemap_ff(RTLIL::Module *module, RTLIL::Cell *cell) +void simplemap_ff(RTLIL::Module *, RTLIL::Cell *cell) { FfData ff(nullptr, cell); for (int i = 0; i < ff.width; i++) { FfData fff = ff.slice({i}); fff.is_fine = true; - fff.emit(module, NEW_ID); + fff.emit(); } } |