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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 12:46:52 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 12:46:52 -0700 |
| commit | 691e145cda416787fe214b5533c6ac3c8047bb65 (patch) | |
| tree | ac78e40defe12c75bcc040f973217ad6875bf5af /passes/techmap/shregmap.cc | |
| parent | 7eec64a38fb9362a43916aec79c7fca04b6ba72c (diff) | |
| parent | 8fa74287a71fc3527cf48c7fb2c4a635ee832b72 (diff) | |
| download | yosys-691e145cda416787fe214b5533c6ac3c8047bb65.tar.gz yosys-691e145cda416787fe214b5533c6ac3c8047bb65.tar.bz2 yosys-691e145cda416787fe214b5533c6ac3c8047bb65.zip | |
Merge branch 'xaig' into xc7mux
Diffstat (limited to 'passes/techmap/shregmap.cc')
| -rw-r--r-- | passes/techmap/shregmap.cc | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 46f6a79fb..21dfe9619 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -293,13 +293,10 @@ struct ShregmapWorker if (opts.init || sigbit_init.count(q_bit) == 0) { - auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell)); - if (!r.second) { + if (sigbit_chain_next.count(d_bit)) { sigbit_with_non_chain_users.insert(d_bit); - Wire *wire = module->addWire(NEW_ID); - module->connect(wire, d_bit); - sigbit_chain_next.insert(std::make_pair(wire, cell)); - } + } else + sigbit_chain_next[d_bit] = cell; sigbit_chain_prev[q_bit] = cell; continue; |