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author | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 10:25:54 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 10:25:54 -0700 |
commit | 02dead2e60e802986ac80137667e399d45233cdc (patch) | |
tree | 13dc1fa37096c7c83159b6403ff703e213be197d /passes/techmap/shregmap.cc | |
parent | 467c34eff05bd62fd64c35f07fe140f33edf4511 (diff) | |
download | yosys-02dead2e60e802986ac80137667e399d45233cdc.tar.gz yosys-02dead2e60e802986ac80137667e399d45233cdc.tar.bz2 yosys-02dead2e60e802986ac80137667e399d45233cdc.zip |
ID(\\.*) -> ID(.*)
Diffstat (limited to 'passes/techmap/shregmap.cc')
-rw-r--r-- | passes/techmap/shregmap.cc | 108 |
1 files changed, 54 insertions, 54 deletions
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index e3f50e354..92637dfa8 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -73,22 +73,22 @@ struct ShregmapTechGreenpak4 : ShregmapTech bool fixup(Cell *cell, dict<int, SigBit> &taps) { - auto D = cell->getPort(ID(\\D)); - auto C = cell->getPort(ID(\\C)); + auto D = cell->getPort(ID(D)); + auto C = cell->getPort(ID(C)); - auto newcell = cell->module->addCell(NEW_ID, ID(\\GP_SHREG)); - newcell->setPort(ID(\\nRST), State::S1); - newcell->setPort(ID(\\CLK), C); - newcell->setPort(ID(\\IN), D); + auto newcell = cell->module->addCell(NEW_ID, ID(GP_SHREG)); + newcell->setPort(ID(nRST), State::S1); + newcell->setPort(ID(CLK), C); + newcell->setPort(ID(IN), D); int i = 0; for (auto tap : taps) { - newcell->setPort(i ? ID(\\OUTB) : ID(\\OUTA), tap.second); - newcell->setParam(i ? ID(\\OUTB_TAP) : ID(\\OUTA_TAP), tap.first + 1); + newcell->setPort(i ? ID(OUTB) : ID(OUTA), tap.second); + newcell->setParam(i ? ID(OUTB_TAP) : ID(OUTA_TAP), tap.first + 1); i++; } - cell->setParam(ID(\\OUTA_INVERT), 0); + cell->setParam(ID(OUTA_INVERT), 0); return false; } }; @@ -105,18 +105,18 @@ struct ShregmapTechXilinx7 : ShregmapTech for (const auto &i : module->cells_) { auto cell = i.second; if (cell->type == ID($shiftx)) { - if (cell->getParam(ID(\\Y_WIDTH)) != 1) continue; + if (cell->getParam(ID(Y_WIDTH)) != 1) continue; int j = 0; - for (auto bit : sigmap(cell->getPort(ID(\\A)))) + for (auto bit : sigmap(cell->getPort(ID(A)))) sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, j++, 0); - log_assert(j == cell->getParam(ID(\\A_WIDTH)).as_int()); + log_assert(j == cell->getParam(ID(A_WIDTH)).as_int()); } else if (cell->type == ID($mux)) { int j = 0; - for (auto bit : sigmap(cell->getPort(ID(\\A)))) + for (auto bit : sigmap(cell->getPort(ID(A)))) sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 0, j++); j = 0; - for (auto bit : sigmap(cell->getPort(ID(\\B)))) + for (auto bit : sigmap(cell->getPort(ID(B)))) sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 1, j++); } } @@ -128,9 +128,9 @@ struct ShregmapTechXilinx7 : ShregmapTech if (it == sigbit_to_shiftx_offset.end()) return; if (cell) { - if (cell->type == ID($shiftx) && port == ID(\\A)) + if (cell->type == ID($shiftx) && port == ID(A)) return; - if (cell->type == ID($mux) && port.in(ID(\\A), ID(\\B))) + if (cell->type == ID($mux) && port.in(ID(A), ID(B))) return; } sigbit_to_shiftx_offset.erase(it); @@ -178,17 +178,17 @@ struct ShregmapTechXilinx7 : ShregmapTech // Only map if $shiftx exclusively covers the shift register if (shiftx->type == ID($shiftx)) { - if (GetSize(taps) > shiftx->getParam(ID(\\A_WIDTH)).as_int()) + if (GetSize(taps) > shiftx->getParam(ID(A_WIDTH)).as_int()) return false; // Due to padding the most significant bits of A may be 1'bx, // and if so, discount them - if (GetSize(taps) < shiftx->getParam(ID(\\A_WIDTH)).as_int()) { - const SigSpec A = shiftx->getPort(ID(\\A)); - const int A_width = shiftx->getParam(ID(\\A_WIDTH)).as_int(); + if (GetSize(taps) < shiftx->getParam(ID(A_WIDTH)).as_int()) { + const SigSpec A = shiftx->getPort(ID(A)); + const int A_width = shiftx->getParam(ID(A_WIDTH)).as_int(); for (int i = GetSize(taps); i < A_width; ++i) if (A[i] != RTLIL::Sx) return false; } - else if (GetSize(taps) != shiftx->getParam(ID(\\A_WIDTH)).as_int()) + else if (GetSize(taps) != shiftx->getParam(ID(A_WIDTH)).as_int()) return false; } else if (shiftx->type == ID($mux)) { @@ -210,32 +210,32 @@ struct ShregmapTechXilinx7 : ShregmapTech auto newcell = cell->module->addCell(NEW_ID, ID($__XILINX_SHREG_)); newcell->set_src_attribute(cell->get_src_attribute()); - newcell->setParam(ID(\\DEPTH), cell->getParam(ID(\\DEPTH))); - newcell->setParam(ID(\\INIT), cell->getParam(ID(\\INIT))); - newcell->setParam(ID(\\CLKPOL), cell->getParam(ID(\\CLKPOL))); - newcell->setParam(ID(\\ENPOL), cell->getParam(ID(\\ENPOL))); + newcell->setParam(ID(DEPTH), cell->getParam(ID(DEPTH))); + newcell->setParam(ID(INIT), cell->getParam(ID(INIT))); + newcell->setParam(ID(CLKPOL), cell->getParam(ID(CLKPOL))); + newcell->setParam(ID(ENPOL), cell->getParam(ID(ENPOL))); - newcell->setPort(ID(\\C), cell->getPort(ID(\\C))); - newcell->setPort(ID(\\D), cell->getPort(ID(\\D))); - if (cell->hasPort(ID(\\E))) - newcell->setPort(ID(\\E), cell->getPort(ID(\\E))); + newcell->setPort(ID(C), cell->getPort(ID(C))); + newcell->setPort(ID(D), cell->getPort(ID(D))); + if (cell->hasPort(ID(E))) + newcell->setPort(ID(E), cell->getPort(ID(E))); Cell* shiftx = std::get<0>(it->second); RTLIL::SigSpec l_wire, q_wire; if (shiftx->type == ID($shiftx)) { - l_wire = shiftx->getPort(ID(\\B)); - q_wire = shiftx->getPort(ID(\\Y)); - shiftx->setPort(ID(\\Y), cell->module->addWire(NEW_ID)); + l_wire = shiftx->getPort(ID(B)); + q_wire = shiftx->getPort(ID(Y)); + shiftx->setPort(ID(Y), cell->module->addWire(NEW_ID)); } else if (shiftx->type == ID($mux)) { - l_wire = shiftx->getPort(ID(\\S)); - q_wire = shiftx->getPort(ID(\\Y)); - shiftx->setPort(ID(\\Y), cell->module->addWire(NEW_ID)); + l_wire = shiftx->getPort(ID(S)); + q_wire = shiftx->getPort(ID(Y)); + shiftx->setPort(ID(Y), cell->module->addWire(NEW_ID)); } else log_abort(); - newcell->setPort(ID(\\Q), q_wire); - newcell->setPort(ID(\\L), l_wire); + newcell->setPort(ID(Q), q_wire); + newcell->setPort(ID(L), l_wire); return false; } @@ -263,16 +263,16 @@ struct ShregmapWorker { for (auto wire : module->wires()) { - if (wire->port_output || wire->get_bool_attribute(ID(\\keep))) { + if (wire->port_output || wire->get_bool_attribute(ID(keep))) { for (auto bit : sigmap(wire)) { sigbit_with_non_chain_users.insert(bit); if (opts.tech) opts.tech->non_chain_user(bit, nullptr, {}); } } - if (wire->attributes.count(ID(\\init))) { + if (wire->attributes.count(ID(init))) { SigSpec initsig = sigmap(wire); - Const initval = wire->attributes.at(ID(\\init)); + Const initval = wire->attributes.at(ID(init)); for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++) if (initval[i] == State::S0 && !opts.zinit) sigbit_init[initsig[i]] = false; @@ -283,7 +283,7 @@ struct ShregmapWorker for (auto cell : module->cells()) { - if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute(ID(\\keep))) + if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute(ID(keep))) { IdString d_port = opts.ffcells.at(cell->type).first; IdString q_port = opts.ffcells.at(cell->type).second; @@ -474,7 +474,7 @@ struct ShregmapWorker initval.push_back(State::S0); remove_init.insert(bit); } - first_cell->setParam(ID(\\INIT), initval); + first_cell->setParam(ID(INIT), initval); } if (opts.zinit) @@ -497,13 +497,13 @@ struct ShregmapWorker if (first_cell->type == ID($_DFFE_PP_)) param_clkpol = 1, param_enpol = 1; log_assert(param_clkpol >= 0); - first_cell->setParam(ID(\\CLKPOL), param_clkpol); - if (opts.ffe) first_cell->setParam(ID(\\ENPOL), param_enpol); + first_cell->setParam(ID(CLKPOL), param_clkpol); + if (opts.ffe) first_cell->setParam(ID(ENPOL), param_enpol); } first_cell->type = shreg_cell_type_str; first_cell->setPort(q_port, last_cell->getPort(q_port)); - first_cell->setParam(ID(\\DEPTH), depth); + first_cell->setParam(ID(DEPTH), depth); if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict)) remove_cells.insert(first_cell); @@ -521,18 +521,18 @@ struct ShregmapWorker for (auto wire : module->wires()) { - if (wire->attributes.count(ID(\\init)) == 0) + if (wire->attributes.count(ID(init)) == 0) continue; SigSpec initsig = sigmap(wire); - Const &initval = wire->attributes.at(ID(\\init)); + Const &initval = wire->attributes.at(ID(init)); for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++) if (remove_init.count(initsig[i])) initval[i] = State::Sx; if (SigSpec(initval).is_fully_undef()) - wire->attributes.erase(ID(\\init)); + wire->attributes.erase(ID(init)); } remove_cells.clear(); @@ -717,19 +717,19 @@ struct ShregmapPass : public Pass { bool en_neg = enpol == "neg" || enpol == "any" || enpol == "any_or_none"; if (clk_pos && en_none) - opts.ffcells[ID($_DFF_P_)] = make_pair(IdString(ID(\\D)), IdString(ID(\\Q))); + opts.ffcells[ID($_DFF_P_)] = make_pair(IdString(ID(D)), IdString(ID(Q))); if (clk_neg && en_none) - opts.ffcells[ID($_DFF_N_)] = make_pair(IdString(ID(\\D)), IdString(ID(\\Q))); + opts.ffcells[ID($_DFF_N_)] = make_pair(IdString(ID(D)), IdString(ID(Q))); if (clk_pos && en_pos) - opts.ffcells[ID($_DFFE_PP_)] = make_pair(IdString(ID(\\D)), IdString(ID(\\Q))); + opts.ffcells[ID($_DFFE_PP_)] = make_pair(IdString(ID(D)), IdString(ID(Q))); if (clk_pos && en_neg) - opts.ffcells[ID($_DFFE_PN_)] = make_pair(IdString(ID(\\D)), IdString(ID(\\Q))); + opts.ffcells[ID($_DFFE_PN_)] = make_pair(IdString(ID(D)), IdString(ID(Q))); if (clk_neg && en_pos) - opts.ffcells[ID($_DFFE_NP_)] = make_pair(IdString(ID(\\D)), IdString(ID(\\Q))); + opts.ffcells[ID($_DFFE_NP_)] = make_pair(IdString(ID(D)), IdString(ID(Q))); if (clk_neg && en_neg) - opts.ffcells[ID($_DFFE_NN_)] = make_pair(IdString(ID(\\D)), IdString(ID(\\Q))); + opts.ffcells[ID($_DFFE_NN_)] = make_pair(IdString(ID(D)), IdString(ID(Q))); if (en_pos || en_neg) opts.ffe = true; |