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| author | David Shah <dave@ds0.me> | 2019-08-30 13:57:15 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-08-30 13:57:15 +0100 |
| commit | 6919c0f9b010c94a0a1a31cd788301e78a1bcbfb (patch) | |
| tree | 4780799b6c1dc1d150b80aa142e6c53e06760cb3 /passes/techmap/nlutmap.cc | |
| parent | edff79a25a802e5b1816608b48e3ac335ad87147 (diff) | |
| parent | 694e30a35426b9582a1f2db730528d4d34305795 (diff) | |
| download | yosys-6919c0f9b010c94a0a1a31cd788301e78a1bcbfb.tar.gz yosys-6919c0f9b010c94a0a1a31cd788301e78a1bcbfb.tar.bz2 yosys-6919c0f9b010c94a0a1a31cd788301e78a1bcbfb.zip | |
Merge branch 'master' into xc7dsp
Diffstat (limited to 'passes/techmap/nlutmap.cc')
| -rw-r--r-- | passes/techmap/nlutmap.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/techmap/nlutmap.cc b/passes/techmap/nlutmap.cc index cc765d89c..798d82248 100644 --- a/passes/techmap/nlutmap.cc +++ b/passes/techmap/nlutmap.cc @@ -82,10 +82,10 @@ struct NlutmapWorker for (auto cell : module->cells()) { - if (cell->type != "$lut" || mapped_cells.count(cell)) + if (cell->type != ID($lut) || mapped_cells.count(cell)) continue; - if (GetSize(cell->getPort("\\A")) == lut_size || lut_size == 2) + if (GetSize(cell->getPort(ID::A)) == lut_size || lut_size == 2) candidate_ratings[cell] = 0; for (auto &conn : cell->connections()) @@ -119,7 +119,7 @@ struct NlutmapWorker if (config.assert_mode) { for (auto cell : module->cells()) - if (cell->type == "$lut" && !mapped_cells.count(cell)) + if (cell->type == ID($lut) && !mapped_cells.count(cell)) log_error("Insufficient number of LUTs to map all logic cells!\n"); } |