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authorAman Goel <amangoel@umich.edu>2019-09-27 12:30:27 -0400
committerGitHub <noreply@github.com>2019-09-27 12:30:27 -0400
commitcb0dc6e68b9432edc9c30c153954be53c8576911 (patch)
treec137f970f949117d04632158d73bfe1f9c146e6f /passes/techmap/insbuf.cc
parent4d343fc1cdafe469484846051680ca0b1f948549 (diff)
parent4b15cf5f76e2226bbce1a73d1e0ff54fbf093fe8 (diff)
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Merge pull request #7 from YosysHQ/master
Syncing with official repo
Diffstat (limited to 'passes/techmap/insbuf.cc')
-rw-r--r--passes/techmap/insbuf.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/insbuf.cc b/passes/techmap/insbuf.cc
index aa81468dc..2173049b4 100644
--- a/passes/techmap/insbuf.cc
+++ b/passes/techmap/insbuf.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct InsbufPass : public Pass {
InsbufPass() : Pass("insbuf", "insert buffer cells for connected wires") { }
- virtual void help()
+ void help() YS_OVERRIDE
{
log("\n");
log(" insbuf [options] [selection]\n");
@@ -37,7 +37,7 @@ struct InsbufPass : public Pass {
log(" call to \"clean\" will remove all $_BUF_ in the design.)\n");
log("\n");
}
- virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
log_header(design, "Executing INSBUF pass (insert buffer cells for connected wires).\n");