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| author | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-04-09 05:24:37 +0000 |
|---|---|---|
| committer | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-04-09 05:28:32 +0000 |
| commit | 83222193afbd70b753f627367b1b3867ba651687 (patch) | |
| tree | 86cf41886498b32e7f86c3c3f1fe3ddde452807d /passes/techmap/hilomap.cc | |
| parent | 42e7e4420768ae4bdf0a7ae32234a9c10939c8f0 (diff) | |
| download | yosys-83222193afbd70b753f627367b1b3867ba651687.tar.gz yosys-83222193afbd70b753f627367b1b3867ba651687.tar.bz2 yosys-83222193afbd70b753f627367b1b3867ba651687.zip | |
Clean up `passes/techmap/hilomap.cc`.
Diffstat (limited to 'passes/techmap/hilomap.cc')
| -rw-r--r-- | passes/techmap/hilomap.cc | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc index 9ec651aef..5aeb5ea79 100644 --- a/passes/techmap/hilomap.cc +++ b/passes/techmap/hilomap.cc @@ -105,13 +105,9 @@ struct HilomapPass : public Pass { } extra_args(args, argidx, design); - for (auto &it : design->modules_) + for (auto mod : design->selected_modules()) { - module = it.second; - - if (!design->selected(module)) - continue; - + module = mod; last_hi = RTLIL::State::Sm; last_lo = RTLIL::State::Sm; |