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| author | Robert Ou <rqou@robertou.com> | 2017-09-12 14:21:04 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-09-14 12:54:44 -0700 |
| commit | ab1bf8d661d3edd865c1b425535b81e8fba9d58d (patch) | |
| tree | 0fbc866fecd9c8563265a5730ec79b9143b2de66 /passes/techmap/extract_reduce.cc | |
| parent | f9d023c53fedd96ec1b9d3a93d0448291a1f2527 (diff) | |
| download | yosys-ab1bf8d661d3edd865c1b425535b81e8fba9d58d.tar.gz yosys-ab1bf8d661d3edd865c1b425535b81e8fba9d58d.tar.bz2 yosys-ab1bf8d661d3edd865c1b425535b81e8fba9d58d.zip | |
extract_reduce: Fix segfault on "undriven" inputs
This is easily triggered when un-techmapping if the technology-specific
cell library isn't loaded. Outputs of technology-specific cells will be
seen as inputs, and nets using those outputs will be seen as undriven.
Just ignore these cells because they can't be part of a reduce chain
anyways.
Diffstat (limited to 'passes/techmap/extract_reduce.cc')
| -rw-r--r-- | passes/techmap/extract_reduce.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc index 114015c23..54e45f836 100644 --- a/passes/techmap/extract_reduce.cc +++ b/passes/techmap/extract_reduce.cc @@ -160,7 +160,7 @@ struct ExtractReducePass : public Pass if (sig_to_sink[a[0]].size() + port_sigs.count(a[0]) == 1) { Cell* cell_a = sig_to_driver[a[0]]; - if (((cell_a->type == "$_AND_" && gt == GateType::And) || + if (cell_a && ((cell_a->type == "$_AND_" && gt == GateType::And) || (cell_a->type == "$_OR_" && gt == GateType::Or) || (cell_a->type == "$_XOR_" && gt == GateType::Xor))) { @@ -177,7 +177,7 @@ struct ExtractReducePass : public Pass if (sig_to_sink[b[0]].size() + port_sigs.count(b[0]) == 1) { Cell* cell_b = sig_to_driver[b[0]]; - if (((cell_b->type == "$_AND_" && gt == GateType::And) || + if (cell_b && ((cell_b->type == "$_AND_" && gt == GateType::And) || (cell_b->type == "$_OR_" && gt == GateType::Or) || (cell_b->type == "$_XOR_" && gt == GateType::Xor))) { |