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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-13 08:17:39 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-13 08:17:39 -0700 |
| commit | 432a09af80f7dcba9fd517a001e3a1954c99537e (patch) | |
| tree | 1adf4d0a7cdf929de445b000255dfa8ca23663a5 /passes/techmap/extract_reduce.cc | |
| parent | b567f03c266b0c44d81a24dde2ed538f1db05d4e (diff) | |
| download | yosys-432a09af80f7dcba9fd517a001e3a1954c99537e.tar.gz yosys-432a09af80f7dcba9fd517a001e3a1954c99537e.tar.bz2 yosys-432a09af80f7dcba9fd517a001e3a1954c99537e.zip | |
kernel: SigSpec use more const& + overloads to prevent implicit SigSpec
Diffstat (limited to 'passes/techmap/extract_reduce.cc')
| -rw-r--r-- | passes/techmap/extract_reduce.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc index 11cfddcd9..92c52398c 100644 --- a/passes/techmap/extract_reduce.cc +++ b/passes/techmap/extract_reduce.cc @@ -286,7 +286,7 @@ struct ExtractReducePass : public Pass SigSpec input; for (auto b : input_pool) if (input_pool_intermed.count(b) == 0) - input.append_bit(b); + input.append(b); SigBit output = sigmap(head_cell->getPort(ID::Y)[0]); |