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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-18 21:29:15 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-18 21:29:15 -0700 |
| commit | e34f2de55d9d1ec8cbdd9c1f3e27af678f0fc2df (patch) | |
| tree | 74c0b3ba63fdd678fcfc839dd6d0d39d43cef365 /passes/techmap/extract_fa.cc | |
| parent | f5170a7eda6fddaf482896a2ad67da4bb3131d7b (diff) | |
| parent | 98a54353b7d893752d856b3726853d4921c6aa1f (diff) | |
| download | yosys-e34f2de55d9d1ec8cbdd9c1f3e27af678f0fc2df.tar.gz yosys-e34f2de55d9d1ec8cbdd9c1f3e27af678f0fc2df.tar.bz2 yosys-e34f2de55d9d1ec8cbdd9c1f3e27af678f0fc2df.zip | |
Merge remote-tracking branch 'origin/master' into clifford/testfast
Diffstat (limited to 'passes/techmap/extract_fa.cc')
| -rw-r--r-- | passes/techmap/extract_fa.cc | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc index ff3de1272..29700c37b 100644 --- a/passes/techmap/extract_fa.cc +++ b/passes/techmap/extract_fa.cc @@ -89,7 +89,7 @@ struct ExtractFaWorker ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($_MUX_), ID($_NMUX_), ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) { - SigBit y = sigmap(SigBit(cell->getPort(ID(Y)))); + SigBit y = sigmap(SigBit(cell->getPort(ID::Y))); log_assert(driver.count(y) == 0); driver[y] = cell; } @@ -262,8 +262,8 @@ struct ExtractFaWorker pool<SigBit> new_leaves = leaves; new_leaves.erase(bit); - if (cell->hasPort(ID(A))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(A))))); - if (cell->hasPort(ID(B))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(B))))); + if (cell->hasPort(ID::A)) new_leaves.insert(sigmap(SigBit(cell->getPort(ID::A)))); + if (cell->hasPort(ID::B)) new_leaves.insert(sigmap(SigBit(cell->getPort(ID::B)))); if (cell->hasPort(ID(C))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(C))))); if (cell->hasPort(ID(D))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(D))))); @@ -277,8 +277,8 @@ struct ExtractFaWorker void assign_new_driver(SigBit bit, SigBit new_driver) { Cell *cell = driver.at(bit); - if (sigmap(cell->getPort(ID(Y))) == bit) { - cell->setPort(ID(Y), module->addWire(NEW_ID)); + if (sigmap(cell->getPort(ID::Y)) == bit) { + cell->setPort(ID::Y, module->addWire(NEW_ID)); module->connect(bit, new_driver); } } @@ -395,15 +395,15 @@ struct ExtractFaWorker log(" Created $fa cell %s.\n", log_id(cell)); - cell->setPort(ID(A), f3i.inv_a ? module->NotGate(NEW_ID, A) : A); - cell->setPort(ID(B), f3i.inv_b ? module->NotGate(NEW_ID, B) : B); + cell->setPort(ID::A, f3i.inv_a ? module->NotGate(NEW_ID, A) : A); + cell->setPort(ID::B, f3i.inv_b ? module->NotGate(NEW_ID, B) : B); cell->setPort(ID(C), f3i.inv_c ? module->NotGate(NEW_ID, C) : C); X = module->addWire(NEW_ID); Y = module->addWire(NEW_ID); cell->setPort(ID(X), X); - cell->setPort(ID(Y), Y); + cell->setPort(ID::Y, Y); facache[fakey] = make_tuple(X, Y, cell); } @@ -501,15 +501,15 @@ struct ExtractFaWorker log(" Created $fa cell %s.\n", log_id(cell)); - cell->setPort(ID(A), f2i.inv_a ? module->NotGate(NEW_ID, A) : A); - cell->setPort(ID(B), f2i.inv_b ? module->NotGate(NEW_ID, B) : B); + cell->setPort(ID::A, f2i.inv_a ? module->NotGate(NEW_ID, A) : A); + cell->setPort(ID::B, f2i.inv_b ? module->NotGate(NEW_ID, B) : B); cell->setPort(ID(C), State::S0); X = module->addWire(NEW_ID); Y = module->addWire(NEW_ID); cell->setPort(ID(X), X); - cell->setPort(ID(Y), Y); + cell->setPort(ID::Y, Y); } if (func2.at(key).count(xor2_func)) { |