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| author | Marcin Kościelnicki <marcin@symbioticeda.com> | 2019-11-18 04:16:48 +0100 |
|---|---|---|
| committer | Marcin Kościelnicki <marcin@symbioticeda.com> | 2019-11-18 04:16:48 +0100 |
| commit | 38e72d6e13b908007577b7782078ac8b968496f5 (patch) | |
| tree | 41e77080c67c9d35dff693253234471c2f43a941 /passes/techmap/extract_fa.cc | |
| parent | 527434de493f88d5da64ae216df3b5a85558e47b (diff) | |
| download | yosys-38e72d6e13b908007577b7782078ac8b968496f5.tar.gz yosys-38e72d6e13b908007577b7782078ac8b968496f5.tar.bz2 yosys-38e72d6e13b908007577b7782078ac8b968496f5.zip | |
Fix #1496.
Diffstat (limited to 'passes/techmap/extract_fa.cc')
| -rw-r--r-- | passes/techmap/extract_fa.cc | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc index 29700c37b..9f3bb525b 100644 --- a/passes/techmap/extract_fa.cc +++ b/passes/techmap/extract_fa.cc @@ -262,10 +262,14 @@ struct ExtractFaWorker pool<SigBit> new_leaves = leaves; new_leaves.erase(bit); - if (cell->hasPort(ID::A)) new_leaves.insert(sigmap(SigBit(cell->getPort(ID::A)))); - if (cell->hasPort(ID::B)) new_leaves.insert(sigmap(SigBit(cell->getPort(ID::B)))); - if (cell->hasPort(ID(C))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(C))))); - if (cell->hasPort(ID(D))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(D))))); + for (auto port : {ID::A, ID::B, ID(C), ID(D)}) { + if (!cell->hasPort(port)) + continue; + auto bit = sigmap(SigBit(cell->getPort(port))); + if (!bit.wire) + continue; + new_leaves.insert(bit); + } if (GetSize(new_leaves) > maxbreadth) continue; |