diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-14 16:26:24 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-14 16:26:24 -0700 |
| commit | 1551e14d2d688982f22f416a55a3212796a82421 (patch) | |
| tree | 808d4a1a62043d29e210256b518e5b8896780052 /passes/techmap/extract_fa.cc | |
| parent | 1e47e81869a41cd231693e176dc661751579fc0b (diff) | |
| download | yosys-1551e14d2d688982f22f416a55a3212796a82421.tar.gz yosys-1551e14d2d688982f22f416a55a3212796a82421.tar.bz2 yosys-1551e14d2d688982f22f416a55a3212796a82421.zip | |
AND with an inverted input, causes X{,N}OR output to be inverted too
Diffstat (limited to 'passes/techmap/extract_fa.cc')
| -rw-r--r-- | passes/techmap/extract_fa.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc index b541ceb6b..8f195a90a 100644 --- a/passes/techmap/extract_fa.cc +++ b/passes/techmap/extract_fa.cc @@ -513,13 +513,13 @@ struct ExtractFaWorker } if (func2.at(key).count(xor2_func)) { - SigBit YY = invert_xy ? module->NotGate(NEW_ID, Y) : Y; + SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? module->NotGate(NEW_ID, Y) : Y; for (auto bit : func2.at(key).at(xor2_func)) assign_new_driver(bit, YY); } if (func2.at(key).count(xnor2_func)) { - SigBit YY = invert_xy ? Y : module->NotGate(NEW_ID, Y); + SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? Y : module->NotGate(NEW_ID, Y); for (auto bit : func2.at(key).at(xnor2_func)) assign_new_driver(bit, YY); } |