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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 10:25:54 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 10:25:54 -0700 |
| commit | 02dead2e60e802986ac80137667e399d45233cdc (patch) | |
| tree | 13dc1fa37096c7c83159b6403ff703e213be197d /passes/techmap/extract_fa.cc | |
| parent | 467c34eff05bd62fd64c35f07fe140f33edf4511 (diff) | |
| download | yosys-02dead2e60e802986ac80137667e399d45233cdc.tar.gz yosys-02dead2e60e802986ac80137667e399d45233cdc.tar.bz2 yosys-02dead2e60e802986ac80137667e399d45233cdc.zip | |
ID(\\.*) -> ID(.*)
Diffstat (limited to 'passes/techmap/extract_fa.cc')
| -rw-r--r-- | passes/techmap/extract_fa.cc | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc index 763caf08d..ff3de1272 100644 --- a/passes/techmap/extract_fa.cc +++ b/passes/techmap/extract_fa.cc @@ -89,7 +89,7 @@ struct ExtractFaWorker ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($_MUX_), ID($_NMUX_), ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) { - SigBit y = sigmap(SigBit(cell->getPort(ID(\\Y)))); + SigBit y = sigmap(SigBit(cell->getPort(ID(Y)))); log_assert(driver.count(y) == 0); driver[y] = cell; } @@ -262,10 +262,10 @@ struct ExtractFaWorker pool<SigBit> new_leaves = leaves; new_leaves.erase(bit); - if (cell->hasPort(ID(\\A))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(\\A))))); - if (cell->hasPort(ID(\\B))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(\\B))))); - if (cell->hasPort(ID(\\C))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(\\C))))); - if (cell->hasPort(ID(\\D))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(\\D))))); + if (cell->hasPort(ID(A))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(A))))); + if (cell->hasPort(ID(B))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(B))))); + if (cell->hasPort(ID(C))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(C))))); + if (cell->hasPort(ID(D))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(D))))); if (GetSize(new_leaves) > maxbreadth) continue; @@ -277,8 +277,8 @@ struct ExtractFaWorker void assign_new_driver(SigBit bit, SigBit new_driver) { Cell *cell = driver.at(bit); - if (sigmap(cell->getPort(ID(\\Y))) == bit) { - cell->setPort(ID(\\Y), module->addWire(NEW_ID)); + if (sigmap(cell->getPort(ID(Y))) == bit) { + cell->setPort(ID(Y), module->addWire(NEW_ID)); module->connect(bit, new_driver); } } @@ -391,19 +391,19 @@ struct ExtractFaWorker else { Cell *cell = module->addCell(NEW_ID, ID($fa)); - cell->setParam(ID(\\WIDTH), 1); + cell->setParam(ID(WIDTH), 1); log(" Created $fa cell %s.\n", log_id(cell)); - cell->setPort(ID(\\A), f3i.inv_a ? module->NotGate(NEW_ID, A) : A); - cell->setPort(ID(\\B), f3i.inv_b ? module->NotGate(NEW_ID, B) : B); - cell->setPort(ID(\\C), f3i.inv_c ? module->NotGate(NEW_ID, C) : C); + cell->setPort(ID(A), f3i.inv_a ? module->NotGate(NEW_ID, A) : A); + cell->setPort(ID(B), f3i.inv_b ? module->NotGate(NEW_ID, B) : B); + cell->setPort(ID(C), f3i.inv_c ? module->NotGate(NEW_ID, C) : C); X = module->addWire(NEW_ID); Y = module->addWire(NEW_ID); - cell->setPort(ID(\\X), X); - cell->setPort(ID(\\Y), Y); + cell->setPort(ID(X), X); + cell->setPort(ID(Y), Y); facache[fakey] = make_tuple(X, Y, cell); } @@ -497,19 +497,19 @@ struct ExtractFaWorker else { Cell *cell = module->addCell(NEW_ID, ID($fa)); - cell->setParam(ID(\\WIDTH), 1); + cell->setParam(ID(WIDTH), 1); log(" Created $fa cell %s.\n", log_id(cell)); - cell->setPort(ID(\\A), f2i.inv_a ? module->NotGate(NEW_ID, A) : A); - cell->setPort(ID(\\B), f2i.inv_b ? module->NotGate(NEW_ID, B) : B); - cell->setPort(ID(\\C), State::S0); + cell->setPort(ID(A), f2i.inv_a ? module->NotGate(NEW_ID, A) : A); + cell->setPort(ID(B), f2i.inv_b ? module->NotGate(NEW_ID, B) : B); + cell->setPort(ID(C), State::S0); X = module->addWire(NEW_ID); Y = module->addWire(NEW_ID); - cell->setPort(ID(\\X), X); - cell->setPort(ID(\\Y), Y); + cell->setPort(ID(X), X); + cell->setPort(ID(Y), Y); } if (func2.at(key).count(xor2_func)) { |