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authorAndrew Zonenberg <azonenberg@drawersteak.com>2017-08-30 18:14:22 -0700
committerAndrew Zonenberg <azonenberg@drawersteak.com>2017-08-30 18:15:12 -0700
commited1e3ed39bf15ff9276587325920a329321bdac2 (patch)
tree05480fa94caabddd2e646f679fee0d2109cbdb7c /passes/techmap/extract_counter.cc
parent634f18be961683917ca589bed1a44b8031f06764 (diff)
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extract_counter: Added optimizations to remove unused high-order bits
Diffstat (limited to 'passes/techmap/extract_counter.cc')
-rw-r--r--passes/techmap/extract_counter.cc50
1 files changed, 34 insertions, 16 deletions
diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc
index 6b4ea13e2..540b1593d 100644
--- a/passes/techmap/extract_counter.cc
+++ b/passes/techmap/extract_counter.cc
@@ -387,22 +387,6 @@ void counter_worker(
//Get new cell name
string countname = string("$COUNTx$") + log_id(extract.rwire->name.str());
- //Log it
- total_counters ++;
- string reset_type = "non-resettable";
- if(extract.has_reset)
- {
- //TODO: support other kind of reset
- reset_type = "async resettable";
- }
- log(" Found %d-bit %s down counter %s (counting from %d) for register %s declared at %s\n",
- extract.width,
- reset_type.c_str(),
- countname.c_str(),
- extract.count_value,
- log_id(extract.rwire->name),
- count_reg_src.c_str());
-
//Wipe all of the old connections to the ALU
cell->unsetPort("\\A");
cell->unsetPort("\\B");
@@ -466,6 +450,40 @@ void counter_worker(
cells_to_remove.insert(extract.count_reg);
cells_to_remove.insert(extract.underflow_inv);
+ //Log it
+ total_counters ++;
+ string reset_type = "non-resettable";
+ if(extract.has_reset)
+ {
+ //TODO: support other kind of reset
+ reset_type = "async resettable";
+ }
+ log(" Found %d-bit %s down counter %s (counting from %d) for register %s declared at %s\n",
+ extract.width,
+ reset_type.c_str(),
+ countname.c_str(),
+ extract.count_value,
+ log_id(extract.rwire->name),
+ count_reg_src.c_str());
+
+ //Optimize the counter
+ //If we have no parallel output, and we have redundant bits, shrink us
+ if(extract.pouts.empty())
+ {
+ //TODO: Need to update this when we add support for counters with nonzero reset values
+ //to make sure the reset value fits in our bit space too
+
+ //Optimize it
+ int newbits = ceil(log2(extract.count_value));
+ if(extract.width != newbits)
+ {
+ cell->setParam("\\WIDTH", RTLIL::Const(newbits));
+ log(" Optimizing out %d unused high-order bits (new width is %d)\n",
+ extract.width - newbits,
+ newbits);
+ }
+ }
+
//Finally, rename the cell
cells_to_rename.insert(pair<Cell*, string>(cell, countname));
}