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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-09-04 21:49:56 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-09-14 10:25:51 -0700 |
| commit | c4a70a8cc32e3eefca678d2d0ed569078423f994 (patch) | |
| tree | 52012a6cb88e12edb332f7e0252d4ea47da49ffc /passes/techmap/extract_counter.cc | |
| parent | f9d023c53fedd96ec1b9d3a93d0448291a1f2527 (diff) | |
| download | yosys-c4a70a8cc32e3eefca678d2d0ed569078423f994.tar.gz yosys-c4a70a8cc32e3eefca678d2d0ed569078423f994.tar.bz2 yosys-c4a70a8cc32e3eefca678d2d0ed569078423f994.zip | |
Fixed typo in comment. Fixed bug where extract_counter would create up counters when it meant to create down counters.
Diffstat (limited to 'passes/techmap/extract_counter.cc')
| -rw-r--r-- | passes/techmap/extract_counter.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc index 540b1593d..de374ab2b 100644 --- a/passes/techmap/extract_counter.cc +++ b/passes/techmap/extract_counter.cc @@ -424,12 +424,12 @@ void counter_worker( cell->setPort("\\CLK", extract.clk); cell->setPort("\\OUT", extract.outsig); - //Hook up hard-wired ports (for now CE and up/=down are not supported), default to no parallel output + //Hook up hard-wired ports (for now CE and up/down are not supported), default to no parallel output cell->setParam("\\HAS_POUT", RTLIL::Const(0)); cell->setParam("\\HAS_CE", RTLIL::Const(0)); cell->setParam("\\DIRECTION", RTLIL::Const("DOWN")); cell->setPort("\\CE", RTLIL::Const(1)); - cell->setPort("\\UP", RTLIL::Const(1)); + cell->setPort("\\UP", RTLIL::Const(0)); //Hook up any parallel outputs for(auto load : extract.pouts) |