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authorEddie Hung <eddie@fpgeh.com>2019-04-21 14:24:50 -0700
committerEddie Hung <eddie@fpgeh.com>2019-04-21 14:24:50 -0700
commita3371e118b05eb9bd5dddb1c20758674ae50a803 (patch)
tree2293da584bc545d2b04948e2f5e28aad2d8b0cea /passes/techmap/dfflibmap.cc
parente3f20b17afce26f08b277b757e32c33a473a8571 (diff)
parentf84a84e3f1a27b361c21fcd30fcf50c1a6586629 (diff)
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Merge branch 'master' into map_cells_before_map_luts
Diffstat (limited to 'passes/techmap/dfflibmap.cc')
-rw-r--r--passes/techmap/dfflibmap.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index 274177a68..b5c0498d0 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -664,7 +664,7 @@ struct DfflibmapPass : public Pass {
logmap_all();
for (auto &it : design->modules_)
- if (design->selected(it.second) && !it.second->get_bool_attribute("\\blackbox"))
+ if (design->selected(it.second) && !it.second->get_blackbox_attribute())
dfflibmap(design, it.second, prepare_mode);
cell_mappings.clear();