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| author | Clifford Wolf <clifford@clifford.at> | 2019-08-17 15:01:31 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-17 15:01:31 +0200 |
| commit | 8915f496d97a2e858cbadb265695dd1a54b80ac4 (patch) | |
| tree | 352bd2245f166e0f6679fed971655c7d3df0a7b4 /passes/techmap/dfflibmap.cc | |
| parent | 41191f1ea48437423b4caf81e6af1e3024bb8c7d (diff) | |
| parent | 3b19c3657cda6d972bd3b1c3eeacdfca5fb35de8 (diff) | |
| download | yosys-8915f496d97a2e858cbadb265695dd1a54b80ac4.tar.gz yosys-8915f496d97a2e858cbadb265695dd1a54b80ac4.tar.bz2 yosys-8915f496d97a2e858cbadb265695dd1a54b80ac4.zip | |
Merge pull request #1300 from YosysHQ/eddie/cleanup2
Use ID::{A,B,Y,keep,blackbox,whitebox} instead of ID()
Diffstat (limited to 'passes/techmap/dfflibmap.cc')
| -rw-r--r-- | passes/techmap/dfflibmap.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 7478e020d..b15109cd3 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -485,7 +485,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare if (design->selected(module, it.second) && cell_mappings.count(it.second->type) > 0) cell_list.push_back(it.second); if (it.second->type == ID($_NOT_)) - notmap[sigmap(it.second->getPort(ID(A)))].insert(it.second); + notmap[sigmap(it.second->getPort(ID::A))].insert(it.second); } std::map<std::string, int> stats; @@ -519,8 +519,8 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare sig = module->addWire(NEW_ID, GetSize(old_sig)); if (has_q && has_qn) { for (auto &it : notmap[sigmap(old_sig)]) { - module->connect(it->getPort(ID(Y)), sig); - it->setPort(ID(Y), module->addWire(NEW_ID, GetSize(old_sig))); + module->connect(it->getPort(ID::Y), sig); + it->setPort(ID::Y, module->addWire(NEW_ID, GetSize(old_sig))); } } else { module->addNotGate(NEW_ID, sig, old_sig); |