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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 14:50:10 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 14:50:10 -0700 |
| commit | 52355f5185fe42e28775e897f458b38a439c0ec5 (patch) | |
| tree | 83d8984e70806c9bcc8cd6d72ea81456ca76aba6 /passes/techmap/dfflibmap.cc | |
| parent | 6cd8cace0c1d2a9f7b1f1cd56a223c38a5ea799a (diff) | |
| download | yosys-52355f5185fe42e28775e897f458b38a439c0ec5.tar.gz yosys-52355f5185fe42e28775e897f458b38a439c0ec5.tar.bz2 yosys-52355f5185fe42e28775e897f458b38a439c0ec5.zip | |
Use more ID::{A,B,Y,blackbox,whitebox}
Diffstat (limited to 'passes/techmap/dfflibmap.cc')
| -rw-r--r-- | passes/techmap/dfflibmap.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index c62224f9d..8a378068e 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -485,7 +485,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare if (design->selected(module, it.second) && cell_mappings.count(it.second->type) > 0) cell_list.push_back(it.second); if (it.second->type == ID($_NOT_)) - notmap[sigmap(it.second->getPort(ID(A)))].insert(it.second); + notmap[sigmap(it.second->getPort(ID::A))].insert(it.second); } std::map<std::string, int> stats; @@ -519,8 +519,8 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare sig = module->addWire(NEW_ID, GetSize(old_sig)); if (has_q && has_qn) { for (auto &it : notmap[sigmap(old_sig)]) { - module->connect(it->getPort(ID(Y)), sig); - it->setPort(ID(Y), module->addWire(NEW_ID, GetSize(old_sig))); + module->connect(it->getPort(ID::Y), sig); + it->setPort(ID::Y, module->addWire(NEW_ID, GetSize(old_sig))); } } else { module->addNotGate(NEW_ID, sig, old_sig); |